1. Field of the Invention
The invention relates to computer architectures having two buses operating asynchronously with respect to each other, and more particularly, to techniques for generating a signal on one bus which is synchronous with signals on that bus, in response to an event occurring on the other bus which may be asynchronous with signals occurring on the first bus.
2. Description of Related Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386SX, 80386DX, or 80486 microprocessor manufactured by Intel Corporation. The CPU is coupled to a host or local bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-50 MHz). The host bus includes 16 or 32 data lines, a plurality of address lines, and various control lines. The typical IBM PC AT-compatible platform also includes DRAM main memory, and in many cases cache memory, both coupled to the local bus.
The typical IBM PC AT-compatible computer also includes an I/O bus which is separate and distinct from the local bus. The I/O bus is coupled to the host bus via certain interface circuitry. The I/O bus includes 8, 16 or 32 data lines, a plurality of I/O address lines, as well as control lines. The I/O address space is logically distinct from the memory address space and if the CPU desires to access an I/O address, it does so by activating an MIO# signal to indicate that this is an access to the I/O address space. The interface circuitry recognizes the I/O signals thereby generated by the CPU, performs the desired operation over the I/O bus, and if appropriate, returns results to the CPU over the host bus.
In practice, some I/O addresses may reside physically on the host bus and some memory addresses may reside physically on the I/O bus. The interface circuitry is responsible for recognizing that a memory or I/O address access must be emulated by an access to the other bus, and is responsible for doing such emulation.
In addition to the above elements, a keyboard controller typically is also coupled to the I/O bus, as is a video display controller. A typical IBM PC AT-compatible system may also include a DMA controller which permits peripheral devices on the I/O bus to read or write directly to or from memory, as well as an interrupt controller for transmitting interrupts from various add-on cards to the CPU. The add-on cards are cards which may be plugged into slot connectors coupled to the I/O bus to increase the capabilities of the system.
General information on the various forms of IBM PC AT-compatible computers can be found in IBM, "PC/AT Technical Reference Manual", in Sanchez, "IBM Microcomputers: A Programmer's Handbook" (McGraw-Hill: 1990) and Solari, "AT Bus Design" (San Diego: Annabooks, 1990). See also the various data books and data sheets published by Intel Corporation concerning the structure and use of the iAPX-86 family of microprocessors, including the "i486 Microprocessor Hardware Reference Manual", published by Intel Corporation, copyright date 1990, "386 SX Microprocessor", data sheet, published by Intel Corporation (1990), and "386 DX Microprocessor", data sheet, published by Intel Corporation (1990). All the above references are incorporated herein by reference.
The original IBM PC-AT computer architecture has spawned several architectural variations which themselves have become standards in the microcomputer industry. As explained in the Solari book, above, these standards include ISA ("Industry Standard Architecture") and EISA ("Extended Industry Standard Architecture"). The EISA architecture is intended to be upward compatible from the ISA architecture, meaning that an add-on card built for ISA should work properly if used in an EISA computer.
The host bus in the various PC-AT compatible architectures includes a plurality of address lines and a plurality of data lines, as well as a number of control lines and power and ground. The exact set of lines which make up the host bus is well known in the industry, and may be determined from various sources, including the references cited above. For present purposes, it is sufficient to identify the following signal lines on the local bus ("#" indicates active low):
______________________________________ HA(23:1) or Address lines. For the 80286 and 80386SX, HA(31:2) 24 bits of address are provided. The high order 23 bits are provided on HA(23:1). For the 80386DX and 80486, 32 bits of address are available. The high order 30 bits are provided on HA(31:2). HBHE# & Host Byte High Enable and Host Byte Low HBLE# or Enable, or Host Byte Enables (3:0). For the HBE#(3:0) 80286 and 80386SX, HBLE# can be thought of as equivalent to HA(0) and HBHE# = IBLE#. For the 80386DX and 80486, HBE#(3:0) carries a 1-or-4 decode of the 2 low order address bits. HD(15:0) or Data lines. The 80286 and 80386SX operate HD(31:0) with a 16-bit external data bus, and the 80386DX and 80486 operate with a 32-bit data bus. HM/IO# Memory/IO control line. When asserted low by the CPU, indicates that the address on HA is an I/O address as opposed to a main memory address. HREADY# Acknowledgment to CPU that a current request has been serviced and CPU can start a new cycle. CLK2, CLK CPU clock signal. or HCLK HW/R# Distinguishes host write cycles from host read cycles. HD/C# Distinguishes host data cycles, either memory or I/O, from host control cycles which are: interrupt acknowledge, halt, and instruction fetching. HADS# Indicates that a valid bus cycle definition and address (HW/R#, HD/C#, HM/IO#, HBE0#, HBE1#, HBE2#, HBE3# (or HBHE# and HBLE#) and HA) are being driven on the host bus. HADS# is asserted synchronously with a rising edge of CLK and both stamped and withdrawn synchronously with the next rising edge of CLK. HOLD Bus hold request. Allows another bus master complete control of the CPU bus. In response to HOLD going active the CPU will float most of its output and input/ output pins. HLDA will be asserted after completing the curreng bus cycle, burst cycle or sequence of locked cycles. The CPU will remain in this state until HOLD is de- asserted. HLDA Hold acknowledge. Goes active in response to a hold request presented on the HOLD signal pin. HLDA indicates that the CPU has given the bus to another local bus master. HLDA is driven active in the same clock that the CPU floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold. ______________________________________
In addition, the 80486 microprocessor has an internal cache memory. In order to maintain cache consistency in view of memory writes which an external host bus master may perform, the host bus for an 80486-based PC-AT compatible microcomputer includes the following additional control lines:
______________________________________ EADS# Asserted by an extrenal host master to indicate that a valid external address has been driven onto the HA address lines and that a cache invalidation cycle should be performed. FLUSH# Cache flush input. Forces the 486 microprocessor to flush its entire internal cache. FLUSH# is active low and need only be asserted for one clock. FLUSH# is asynchronous bup setup and hold times must be met for recognition in any specific clock. ______________________________________
The various signals on the I/O bus are also well specified and well known in the industry. They are described in BCPR Services, Inc., "EISA Specification", ver. 3.11 (1990). For present purposes, only the following signals are important:
______________________________________ SA(19:0) 20 address lines. Sufficient to address 1MB of memory. Only SA(15:0) are used to address the 64k I/O address space, and only SA(9:0) are used to address the basic 1k AT I/O address space. LA(31:2) Additional address lines for addressing a 16MB memory address space on the I/O bus. The LA lines are valid earlier in an I/O bus cycle, but must be latched if needed later in the cycle. The SA lines are not valid as early as the LA lines, but remain valid longer. SD(31:0) 32 data lines. BCLK I/O bus clock signal. 6-8.33 MHz signal. Usually a square wave, but the EISA standard specification states that a BCLK cycle can be stretched in certain situations in order to ensure that a desired edge of an EISA bus signal occurs synchronously with a desired edge of BCLK. OSC 14.318 MHz square wave. START# Start a bus cycle. Interface chipset or EISA master activates START# when the address lines LA(31:2) and M/IO are valid. START# terminates in response to the rising edge of BCLK which occurs at least one full BCLK cycle after it was asserted. Sampled on the rising edge of BCLK if necessary. CMD# Indicates when data is valid on the SD lines for write cycles. The leading (falling) edge of CMD# must be synchronous with a rising edge of BCLK and occurs at the same time as the trailing edge of START#. It remains active until the end of the cycle and usually, but not always, terminates synchronously with a rising edge of BCLK. MSBURST# Master Burst. Asserted by an EISA bust master if both the master and the slave are capable of supporting the next cycle as a burst cycle. Sampled on rising edge of BCLK. EXRDY EISA Ready. De-asserted by an EISA slave when it is not ready to terminate an EISA cycle. Sampled on the falling edge of BCLK after CMD# becomes active. If EXRDY is inactive at that time, EXRDY is sampled again on each BCLK falling edge thereafter. CMD# remains active for at least one-half of a BCLK cycle after EXRDY is sampled active, so this signal is useful for generating an "early ready" signal to the CPU. CHRDY ISA Channel Ready. De-asserted by an ISA slave before a falling edge of BCLK if the salve will not be ready to terminate and ISA cycle on the next BCLK rising edge. Sampled on the falling edge of BCLK just prior the BCLK rising edge on which the ISA cycle would otherwise terminate. If CHRDY is low at that time, it is sampled again on each BCLK falling edge thereafter. CMD# remains active for at least one-half BCLK cycle after CHRDY is sampled active, so like EXRDY, CHRDY is useful for logic which generates an "early ready" signal to the CPU. NOWS# ISA No Wait State slave. Asserted by an ISA slave before a BCLK falling edge to shorten default-length ISA cycles. Sampled on BCLK falling edge and if active at that time, will cause CMD# to go inactive on the immediately following BCLK rising edge. If HRDY is low at the time NOWS# is sample active, termination of the cycle is delayed. CMD# will remain active for at least one-half BCLK cycle after NOWS# is sample active, and so NOWS# can be used in logic to generate an "early ready" signal to the CPU. ______________________________________
Recently, efforts have been made to reduce the size and improve the manufacturability of PC AT-compatible computers. Specifically, several manufacturers have developed "PC AT chipsets", which integrate a large amount of the I/O interface circuitry and other circuitry onto only a few chips. An example of such a chipset for ISA microcomputers is the 386WB PC/AT chipset manufactured by OPTi, Inc., Santa Clara, Calif. Examples of such a chipset for EISA microcomputers are described in Intel, "82350 EISA Chip Set" (1990) and in Intel, "82350DT EISA Chip Set" (1992), both available from Intel Corp., Santa Clara, Calif., and incorporated by reference herein. Another example of such a chipset for EISA microcomputers is described in Buchanan, "A Highly Integrated VLSI Chip Set For EISA System Design", Silicon Valley Personal Computer Design Conference Proceedings, Jul. 9-10, 1991, pp. 293-306.
In the original IBM PC AT computer manufactured by IBM Corp., the I/O bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate with on the local bus. Numerous third party vendors have since developed peripheral devices and controller cards which are intended to be plugged into an AT, ISA or EISA slot on the I/O bus, and which rely upon the 8 MHz maximum data rate.
In the years since the IBM PC AT was originally introduced, technology has improved dramatically to the point where local buses on typical high-end PC AT-compatible computers can operate on the order of 50 MHz. Despite these advances, however, such computers are still manufactured with an I/O bus operating at around 8 MHz because of the need to maintain compatibility with previously designed peripheral devices. These devices were designed in reliance upon the 8 MHz data rate, and many such devices are not capable of operating faster. Even modern designs for AT bus peripherals often rely on the 8 MHz maximum data rate, even though very little additional effort or cost would be involved to design them to operate faster. The modern EISA bus also operates only at about 8 MHz because of the need to maintain compatibility with add-on cards designed for AT and ISA platforms. Accordingly, efforts to further enhance the performance of EISA bus systems must rely on techniques other than increased BCLK frequencies.
One of the problems that PC-AT-compatible designs encounter arises because an event which occurs on the I/O bus, and which must cause a responsive event on the host bus, must cause such host bus event synchronously with the host bus CLK signal. Otherwise the system risks violating the setup and hold requirements of the CPU input lead. As used herein, a signal or event is considered synchronous with a clock signal if it occurs in response to an edge transition in the clock signal. A signal or event is asynchronous with a clock signal if it is not generated in coordination with any edge transition in the clock signal. An example of a synchronization problem occurs at the end of a CPU read access to an address which is located physically on the EISA bus. At the end of such an EISA read cycle, interface circuitry deactivates the EISA bus CMD# signal in response to a BCLK rising edge. After terminating CMD#, the interface circuitry must assert HREADY# to the CPU synchronously with a rising edge of the host CLK signal. HREADY# is sampled on the following rising edge of CLK, and the interface circuitry withdraws HREADY# at that time as well. Assuming CLK and BCLK operate asynchronously with eath other, in which case the end of CMD# will not occur synchronously with CLK, the interface circuitry must perform a synchronizing function when it asserts HREADY# in response to the termination of CMD# in order to minimize the risk of violating the setup-and-hold requirements of the CPU's RDY# input.
Synchronizers are well known in the art, and a typical synchronizer is depicted in FIG. 1. As shown in FIG. 1, it includes two D flip-flops 102 and 104, each with a D input, a Q output, and a clock input. The Q output of flip-flop 102 is connected to the D input of flip-flop 104. The synchronous output signal is provided on the Q output of flip-flop 104, and the clock signal with which it is synchronized is connected via a line 106 to the clock inputs of both flip-flops 102 and 104. The input signal in response to which the synchronous output signal is generated, is provided to the D input of flip-flop 102. In operation, if the input signal reaches the D input of flip-flop 102 later than one "hold" time t.sub.hold after a rising edge of the clock signal on line 106, and before a "setup" time t.sub.setup prior to the next rising edge of the clock signal on line 106, then the operation of the synchronizer is straightforward. The input signal is loaded into D flip-flop 102 in response to the first clock rising edge which reaches flip-flop 102 after the input signal reaches the D input of flip-flop 102, and appears on the Q output of flip-flop 102 shortly thereafter. It then reaches the D input of flip-flop 104 well before the next rising edge of the clock signal, thereby certainly meeting all setup and hold requirements of flip-flop 104. In response to the second rising edge of the clock signal, the input signal is loaded into flip-flop 104.
If instead the input signal were to reach the D input of flip-flop 102 too close to a rising edge of the clock signal on line 106, however, then the flip-flop 102 may enter a metastable state in which the Q output of flip-flop 102 may either oscillate or approach a stable state only very slowly. The time from t.sub.setup prior to a rising edge, through t.sub.hold after the rising edge, is sometimes called a metastability window and has a duration dependent upon the fabrication technology and the design of the flip-flops. Assuming the timing of the input signal is uncorrelated with the destination clock signal (which would normally be the case when the host clock and BCLK signals are generated asynchronously), each input event to be synchronized has a finite probability, defined by the length of the metastability window divided by the period of a BCLK cycle, of placing flip-flop 102 into a metastable state. If the output of a synchronizer were to be taken from the Q output of flip-flop 102, the synchronizer would not be very reliable due to the relatively large probability of metastable output states. Usually, however, metastable states do become stable after some period of time. The metastable output of flip-flop 102 therefore usually will reach a stable state at the D input of flip-flop 104 before the next clock rising edge arrives at the clock input of flip-flop 104. There is still a possibility that this signal will not settle sufficiently by that time, and that flip-flop 104 will also enter a metastable state, but that probability is significantly less than the probability of a metastable state after only one flip-flop.
Accordingly, the inclusion of the second flip-flop 104 significantly improves the reliability of the synchronizer of FIG. 1. It is known that the longer the time delay between the triggering of flip-flop 102 and the triggering of flip-flop 104, the more reliable the synchronizer. It is also known that the two flip-flops of the synchronizer may be triggered in response to opposite polarity edge transitions in the clock signal on line 106, if the time delay between such opposite polarity edges is long enough, given the design of the flip-flops, to permit most metastable states of the first flip-flop to settle. It is also known that the addition of a third series flip-flop would further improve reliability as would each additional series flip-flop. However, it is generally considered that two series flip-flops are sufficient. Accordingly, it is generally considered that at least two flip-flops and two clock edges of the destination bus clock are required to reliably provide an output signal which is synchronous with the destination bus clock signal in response to an input signal occurring asynchronously with respect to the destination bus clock signal.
Returning to the example in which the interface circuitry generates HREADY# synchronously with a rising edge of CLK in response to the termination of CMD#, if BCLK is generated completely asynchronously with CLK, then the interface circuitry synchronization function requires at least two edges of CLK before HREADY# can be asserted. Since CLK frequencies are high enough that the two edges used for synchronization should be of the same polarity, the synchronizer in the interface circuitry is not able to assert HREADY# until between one and two full CLK cycles after the withdrawal of CMD# reaches the first flip-flop of the synchronizer, depending on whether it does so early or late in the CLK cycle. To improve the throughput of EISA systems, therefore, it is desirable to reduce or eliminate the synchronization delay.
The Intel 82350 chipset, instead of using a BCLK generated asynchronously with the host CLK signal, generates BCLK synchronously with CLK by dividing the CLK signal down. For example, if CLK operates at 25 MHz (40 nS period), the chipset generates BCLK by dividing CLK by 3. If CLK operates at 33 MHz (30 nS), then the chipset generates BCLK by dividing CLK by 4. In both cases, the resulting BCLK frequency is 8.33 MHz (120 nS). Generating BCLK synchronously with CLK avoids the need for synchronization delays in the transmission of signals from one bus to the other, but only if certain other restrictions are satisfied. For example, an EISA bus signal generated synchronously with BCLK may be transmitted directly to the host bus without a synchronization circuit only if the signal will reach the CPU prior to the setup time before the CLK edge on which the signal will be sampled. Thus the total time delay from a rising edge of CLK, through the frequency divider to a rising edge of BCLK, plus the time delay inserted by the internal interface chipset circuitry (as in the case of CMD#), from the BCLK rising edge to the time it asserts the signal to be transmitted to the host bus, plus the CPU setup time for the signal, must all total less than the period of one CLK cycle. For a host CLK frequency of 33 MHz (30 nS), this restriction can impose a severe limitation on the design of EISA system board circuitry. For host clocks operating at 50 MHz (20 nS), the restriction can be impossible to satisfy.
For some signals to be transmitted from the EISA bus to the host bus, it may be possible to relax the restriction by having the interface circuitry generate the host bus signal in response to a different signal occurring either on the EISA bus or internally to the chipset, which predicts the occurrence of the particular signal half or one BCLK cycle later. For example, it is believed that the Intel 82350 chipset generates HREADY# at the end of an EISA read cycle in response to the detection by the chipset of the EISA bus EXRDY signal sampled active on a falling edge of BCLK after CMD# became active. (With reference to ISA cycles, it is believed that the Intel 82350 chipset generates HREADY# at the end of an ISA read cycle in response to CMD# and CHRDY both sampled active on a BCLK falling edge after the minimum CMD# width is satisfied, and also in response to NOWS#, CMD# and CHRDY all sampled active on a BCLK falling edge whether or not the minimum CMD# width has been satisfied.) EISA slave devices keep EXRDY asserted, and withdraw the signal prior to a BCLK falling edge only if the device does not expect to be able to terminate the cycle in response to the immediately following BCLK rising edge. Therefore, EXRDY sampled active on a falling edge of BCLK after CMD# has become active, predicts that CMD# will be withdrawn in response to the immediately following BCLK rising edge. Accordingly, it is believed that the 82350 chipset generates HREADY# by detecting EXRDY active in response to a BCLK falling edge while CMD# is active, then asserts HREADY# in response to the second host CLK rising edge thereafter. Whether the CLK signal operates at 25 MHz or 33 MHz, a two CLK delay assures that HREADY# will be asserted no earlier than the time that CMD# is withdrawn. The EXRDY-sampling-to-HREADY# delay in the 83250 chipset is believed to be fixed at two CLK cycles, regardless of the CLK clock frequency.
This solution may relieve the timing restrictions on CMD#, but merely reapplies them to the generation of BCLK falling edges. That is, although the time delay restrictions for CMD# no longer apply since withdrawal of CMD# is no longer used to generate HREADY#, new timing restrictions are placed on the BCLK falling edge similar to those which previously applied to CMD#. These restrictions BCLK are not required necessarily for accurate generation of HREADY#, since the two CLK period delay essentially creates a de-facto synchronizer. However, early availability of EXRDY makes it desirable to generate an "early ready" signal for the host bus in case the host bus circuitry inserts a clocked delay before the host bus cycle can be terminated. It has in fact become nearly a market requirement that I/O interface chipsets have an "early ready" signal available. Early ready is asserted only one CLK cycle following detection of EXRDY sampled active with CMD# active in the Intel 82350 chipset, thereby permitting only a one cycle synchronization delay. As previously explained, a single flip-flop is generally considered insufficient for reliable synchronization with minimal probability of metastability. Accordingly, the specification for the Intel 82350 chipset still mandates that BCLK falling edges, as provided to the BCLK input of the chipset from the BCLK output of the chipset, occur no more than 15 nS after a CLK rising edge. Since the chipset requires all 15 nS to generate the BCLK falling edges, and since no discrepancy is permitted between the BCLK signal as provided to the BCLK input and the BCLK signal as actually used on the bus, this imposes a severe restriction indeed on board layout and routing of the BCLK signal.
For signals being transmitted from the host bus to the I/O bus, a similar synchronization problem exists. If an event must occur on the EISA bus in response to an event on the host bus, the I/O interface circuitry must take steps to ensure that the EISA bus event will be synchronous with an edge of BCLK; otherwise the system risks violating the setup and hold requirements of EISA bus devices.
When the CPU issues a memory or I/O read access to an address which is present physically on the EISA bus, it does so by setting up the address and cycle definition control lines on the host bus, and then asserting the host bus HADS# signal synchronously with a rising edge of the host clock signal. HADS# remains active for one full CLK cycle, and then terminates synchronously with the next rising edge of CLK, the edge on which ADS# is intended to be sampled. The interface circuitry recognizes that the access is to an address physically present on the EISA bus. The interface circuitry sets up appropriate cycle definition signals on the EISA bus, and then asserts START# to start the EISA read cycle. START# is specified to be sampled on a rising edge of BCLK. The EISA specification also calls for START# to terminate synchronously with the BCLK rising edge on which it is sampled. The EISA specification further requires START# to remain asserted for at least 120 nS (approximately one BCLK cycle time). Essentially, therefore, assuming no alteration of the BCLK signal itself, START# must be asserted synchronously with one rising edge of BCLK and withdrawn synchronously with the next rising edge of BCLK. The interface circuitry therefore must take steps to ensure that START# will be asserted and withdrawn synchronously with BCLK.
Assuming BCLK is generated asynchronously with CLK, then the interface circuitry synchronization function requires at least two edges of BCLK before START# could be asserted. The period of the BCLK signal is long enough such that these two edges can be opposite polarity edges of BCLK, but even so, the delay from detection of ADS# to assertion of START# can still be significant. Assuming a 120 nS BCLK period (8.33 MHz), this delay can be anywhere from 60 nS (if ADS# reaches the input of the first synchronizer flip-flop just before a falling edge of BCLK) to 180 nS (if the ADS# signal reaches the first synchronizer flip-flop just after a falling edge of BCLK. Such a delay can significantly affect a system-level throughput.
The Intel 82350 chipset avoids this delay for signals being transmitted from the host bus to the EISA bus since, as mentioned above, it generates BCLK synchronously with the host CLK signal. For these situations, for certain signals, other techniques are known for improving system throughput. For example, the Intel 82350 chipset uses a BCLK stretching technique (contemplated by the EISA standards committee) for the generation of START# at the beginning of an EISA cycle. The technique takes advantage of the fact that with a synchronously generated BCLK, there are only three or four possible cases of the relationship of HADS# to BCLK, depending on whether the CLK is divided by four or three, respectively, to generate BCLK. In this technique, HADS# is sampled active on a rising edge of CLK. On the next rising edge of CLK, regardless of the state of BCLK, the chipset asserts START#. It de-asserts START# in response to the fourth (or third) CLK rising edge thereafter, depending on the CLK frequency, thereby ensuring that START# has remained active for at least the required 120 nS. Then, in order to preclude any BCLK rising edge prior to the CLK edge in response to which START# is de-asserted, the following algorithm is followed: (1) If BCLK is high after START# is asserted, BCLK is maintained high until half a BCLK time before START# will end. The BCLK signal is then allowed to go low and continue normally. (2) If BCLK is low following the assertion of START#, then BCLK is maintained low until the end of START#. In all cases, BCLK has its first rising edge, after START# is asserted, in response to the same CLK rising edge to which the de-assertion of START# is responsive. The technique thereby keeps the START# to its minimum time period and thereby enhances throughput. It can be seen that BCLK stretching can be used only where the chipset generates BCLK, such as where the chipset generates BCLK synchronously with CLK.
The 80386-compatible and 80486-compatible CPUs, which are the most appropriate CPUs for use with an EISA architecture, are available operating at frequencies of at least 20 MHz, 25 MHz, 33 MHz, 40 MHz and 50 MHz. The EISA bus specification permits BCLK frequencies of up to 8.33 MHz (120 nS), and it is naturally advantageous to operate the EISA bus at the highest permitted frequency. Although a BCLK of 8.33 MHz is easily derived from CLK frequencies of 25 MHz or 50 MHz, by dividing by 3 or 6, respectively, the closest one can come by simple division of a 33 MHz signal is 8.25 MHz (division by 4). Similarly, the closest one can come by simple division of a 40 MHz signal is 8.0 MHz (division by 5). And for CLK frequencies of 20 MHz, the closest one can come to 8.33 MHz by simple division can deviate significantly from that maximum. Accordingly, for this host CLK frequency, an asynchronously generated BCLK may actually have higher system throughput than a synchronously generated BCLK signal even after synchronization delay requirements are considered.